Improvements, which have been performed vigorously for the MIS-type semiconductor devices, include optimization of the threshold gate voltage, reduction of the channel resistance, increase of the interrupting current, reduction of the leakage current, strengthening of the avalanche withstanding capability, and reduction of the switching loss. The examples that have improved these items will be described below.
FIG. 27 is a cross sectional view of a conventional MIS-type semiconductor device that prevents lowering of the threshold gate voltage when the channel is shortened (when the channel width is narrowed), reduces the deviations of the threshold gate voltage caused by irregular machining of the gate, and exhibits a high mobility, as disclosed in Japanese Unexamined Laid Open Patent Application H06 (1994)-29522. Here, the conventional MIS-type semiconductor device includes a channel region, the surface portion thereof is doped lightly. Hereinafter, the lightly doped surface portion of the channel region will be referred to as the “lightly doped surface layer 105.” The conventional MIS-type semiconductor device further includes buried layers 106, 107 formed below lightly doped surface layer 105, which buried layers are doped more heavily than lightly doped surface layer 105. The heavily doped buried layers 106, 107 are formed more shallowly than the depletion layer expanding from the surface of the semiconductor chip when an inversion layer is formed in the lightly doped surface layer 105. The buried layers 107, 107, extended from the channel edge for a certain distance LP into the channel region, are doped more heavily than the buried layer 106 positioned in the center of the channel region (between the buried layers 107, 107).
In the structure described above, the lowering of the threshold gate voltage caused by the shortened channel length is compensated by the rise of the threshold gate voltage due to the extension of heavily doped buried layers 107, 107 for the distance LP. Since the surface layer 105, in which a channel is formed, is doped lightly, a high mobility is realized. FIG. 27 also illustrates a silicon substrate 101, element separation films 102, a gate electrode 103, source/drain layers 104, interlayer insulation films 108, aluminum wiring layers 110, and a gate insulation film 111.
FIG. 28 is a cross sectional view of a conventional SiC (silicon carbide) trench MOSFET, in which a gate electrode is buried in a trench. The conventional trench MOSFET shown in FIG. 28 increases the controllable current, improving the avalanche withstanding capability, and reducing the ON-resistance, as disclosed in Japanese Unexamined Laid Open Patent Application H09 (1997)-36359. Here, the conventional trench MOSFET includes a trench 215, a p-type base region 213, and a p+-type buried region 220, which is doped more heavily than the p-type base region 213 and formed in the p-type base region 213, but not in the vicinity of the trench 215. This structure lowers the substantial resistance of the p-type base region 213 and increases the controllable current. A p+-type buried layer (not illustrated) formed below the bottom of the trench 215 promotes depletion layer expansion when a voltage is applied, preventing dielectric breakdown of the gate insulation film, and improving the avalanche withstanding capability. FIG. 28 also illustrates an n+-type substrate 211, an n-type drift layer 212, a source layer 214, a gate oxide film 216, a gate electrode 217, a source electrode 218, and a drain electrode 219.
FIG. 29 is a cross sectional view of a conventional MOSFET that suppresses the leakage current, as disclosed in Japanese Unexamined Laid Open Patent Application 2002-9283. Here, the conventional MOSFET includes a well region 301, a heavily doped drain region 302 in the surface portion of the well region 301, a lightly doped drain region 303 in another surface portion of the well region 301, and an impurity region 315 below the heavily doped drain region 302 and the lightly doped drain region 303. The impurity region 315 is provided with a polarity opposite to the polarity of the drain regions 302, 303 and doped more heavily than the well region 301 so that the depletion layer between the drain regions 302, 303 and the well region 301 can be prevented from expanding toward the well region 301. Since this structure prevents especially the depletion layer below the lightly doped drain region 303 from expanding toward the well region 301, this structure is very effective to suppress the current flowing through the region deeper than the channel. FIG. 29 also illustrates a heavily doped source region 304, a lightly doped source region 305, a gate electrode 306, a gate oxide film 307, a field oxide film 308, a field doped region 309, an interlayer insulation film 310, a protection film 311, a drain wiring 312, and a source wiring 313.
Now switching loss reduction for the MIS-type semiconductor devices will be described. The feedback capacitance affects greatly the switching characteristics of the MIS-type semiconductor devices. It has been known to reduce the feedback capacitance to reduce the energy loss in switching. Therefore, it is necessary for the conventional MIS-type semiconductor devices to minimize the overlapping area between the gate electrode and the drift region so that the capacitance between the gate and the drain, that is the feedback capacitance, can be reduced. Note that the feedback capacitance becomes larger as the depletion region (the length in the cross sectional view FIG. 29) expanding in the boundary portion of the semiconductor chip in the vicinity of the gate insulation film beneath the gate electrode becomes larger (longer).
The lateral trench MISFET disclosed in Japanese Unexamined Laid Open Patent Application H08 (1996)-181313 is manufactured through the following steps. First, trenches are formed in a semiconductor substrate. Then, a drain region is formed in the bottom portion of the trench. Then, a drift region is formed around the trench with an oxide film interposed therebetween. Then, a base region is formed in the surface portion of the semiconductor chip such that the base region is spaced apart from the trench. Then, an emitter region is formed in the surface portion of the base region. Then, a gate oxide film is formed on the extended portion of the base region extended between the emitter region and the drift region. Finally, a gate electrode is formed on the gate oxide film. The gate oxide film formed on the semiconductor chip is very uniform and very reliable. By forming the drain region in the bottom portion of the trench, the unit cell size, the ON-resistance, and the tradeoff relation between the breakdown voltage and the ON-resistance are reduced.
Japanese Examined Patent Application S62 (1987)-41428 discloses a lateral MISFET, which includes a drain region, a lightly doped offset gate region contacting the drain region, a base region, a source region, a gate electrode formed above the extended portion of the base region extended between the source region and the offset gate region with a gate insulation film interposed therebetween, a source electrode connected electrically to the source region, and a heavily doped buried region. One end of the heavily doped buried region is connected electrically to the source electrode, and the conductivity type thereof is opposite to the conductivity type of the drain region. The heavily doped buried region surrounds the source region below the source electrode and the other end of the heavily doped buried region extends to the vicinity of the region beneath the edge of the offset gate region. This structure prevents the switch back phenomena. In the switch back phenomena, the resistance becomes negative in the region (in which the current rises sharply) of the breakdown voltage characteristics, the breakdown voltage lowers sharply, and the drain current increases sharply.
The lateral MISFET disclosed in Japanese Examined Patent Application S63 (1988)-46992 includes offset gate regions formed by the self-alignment technique using a gate electrode as a mask. An end of each offset gate region overlaps with either one of the ends of the gate electrode and the offset gate regions are connected electrically to a source region and a drain region. This structure realizes a high breakdown voltage and a high-density circuit integration.
Since the foregoing drift region is formed usually by diffusion, the donors and the acceptors compensate each other and the effective impurity concentration (the net impurity concentration) becomes low in the boundary between the base region and the drift region. As the overlapping area between the gate electrode and the drift region becomes narrower, only the lightly doped portion of the drift region remains finally overlapping with the gate electrode, and the drift resistance of the lightly doped portion becomes high, causing high ON-resistance. If the patterns are not positioned precisely, the drift region and the gate electrode will not overlap each other, the channel and the drift region will be disconnected, and no electrical conduction will be obtained in some cases.
Accordingly, there remains a need to obviate the problems described above to form MIS-type semiconductor devices exhibiting low ON-resistance and high-speed switching capability. The present invention addresses this need.